1 of 7 general description the DS1100L is a 3.3v version of the ds1100. it is characterized for operation over the range 3.0v to 3.6v. the DS1100L series delay lines have five equally spaced taps providing delays from 4ns to 500ns. these devices are offered in surface - mount packages to save pc b area. low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry - standard max and so packaging. the DS1100L 5 - tap silicon delay line repr oduces the input - logic state at the output after a fixed delay as specified by the extension of the part number after the dash. the DS1100L is designed to reproduce both leading and trailing edges with equal precision. each tap is capable of driving up to 10 74ls loads. maxim can customize standard products to meet special needs. features ? all - silicon timing circuit ? five taps equally spaced ? delays are stable and precise ? both leading - and trailing - edge accuracy ? 3.3v version of the ds1100 ? low - power c mos ? ttl - /cmos - c ompatible ? vapor - phase and ir solderable ? custom delays available ? fast - turn prototypes ? delays specified over both commercial and industrial temperature ranges pin assignment pin description tap 1 to tap 5 - tap output number v cc - +3.3v gnd - ground in - input DS1100L 3.3v 5 - tap economy timing element (delay line) 1 2 3 4 8 7 6 5 v cc tap 1 tap 3 tap 5 in tap 2 tap 4 gnd DS1100Lz so (150 mi l s ) DS1100Lu max? 19-5736 ; rev 3/11 max is a registered trademark of maxim integrated products, inc.
DS1100L 2 of 7 absolute maximum ratings voltage range on any pin relative to ground ........................... - 0.5v t o +6.0v short - circuit output current ...................................................... 50ma for 1s operating temperature range .................................................... - 40c to +85c storage temperature range ........................................................ - 55c to +125c lead temperature (soldering, 10s) .............................................. +300 c soldering temperature (reflow) lead(pb) - free ........................................................................... +260 c containing lead(pb) ................................................................. +240 c this is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. dc electrical characteristics (v cc = 3.0v to 3 .6v; t a = - 40c to +85c , unless otherwise noted .) parameter sym bol condition s min typ max units notes supply voltage v cc 3.0 3.3 3.6 v 5 high - level input voltage v ih 2.0 v cc + 0.3 v 5 low - level input voltage v il - 0.3 0.8 v 5 input - leakage cu rrent i i 0.0v v i v cc - 1.0 + 1.0 a active current i cc v cc = max; freq. = 1mhz 10 ma 6, 8 high - level output current i oh v cc = min. v oh = 2.3 - 1 ma low - level output current i ol v cc = min. v ol = 0.5 8 ma ac electrical characteristics (v cc = 3.0v to 3.6v; t a = - 40c to +85c , unless otherwise noted .) parameter sym bol condition s min typ max units notes input pulse width t wi 20% of tap 5 t plh ns 9 input - to - tap delay tolerance (delays 40ns) t plh, t phl +25c 3.3v - 2 table 1 +2 ns 1, 3 , 4, 7 0c to +70c - 3 table 1 +3 ns 1, 2, 3, 4, 7 - 40c to +85c - 4 table 1 +4 ns 1, 2, 3, 4, 7 input - to - tap delay tolerance (delays > 40ns) t plh, t phl +25c 3.3v - 5 table 1 +5 % 1, 3, 4, 7 0c to +70c - 8 table 1 +8 % 1, 2, 3, 4, 7 - 40c to +85c - 13 table 1 +13 % 1, 2, 3, 4, 7 output rise or fall time t of , t or 2.0 2.5 ns power - up time t pu 200 s input period period 2(t wi ) ns 9 capacitance (t a = +25c , unless otherwise noted. ) parameter symbol conditions min typ max units notes input capacitance c in 5 10 pf
DS1100L 3 of 7 notes: 1) initial tolerances are with respect to the nominal value at +25c and v cc = 3.3v for both leading and trailing edge. 2) temperatu re and voltage tolerance is with respect to the nominal delay value over the stated temperature range, and a supply - voltage range of 3.0v to 3.6v. 3) all tap delays tend to vary unidirectionally with temperature or voltage changes. for example, if tap 1 slows down, all other taps also slow down; tap3 can never be faster than tap2. 4) intermediate delay values are available on a custom basis. for further information, contact the factory at cu stom.oscillators@maxim - ic.com . 5) all voltages are referenced to ground. 6) measured with outputs open. 7) see test conditions section at the end of this data sheet. 8) frequenc ies higher than 1mhz result in higher i cc values. 9) at or near maximum frequency the dela y accuracy can vary and will be application sensitive (i.e., decoupling, layout). figure 1. logic diagram figure 2. timing diagram: silicon delay line
DS1100L 4 of 7 terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge or the 1.5v point on the trailing edge and the 1.5v point on t he leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t pl h (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of any tap output pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of any tap output pulse. test setup description figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100L. the input waveform is produced by a precis ion pulse generator under software control. time delays are measured by a time interval counter (20ps resolution) connected between the input and each tap. each tap is selected and connected to the counter by a vhf switch control unit. all measurements are fully automated, with each instrument controlled by a central computer over an ieee 488 bus. test conditions input: ambient temperature: 25c 3c supply voltage (v cc ): 3.3v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ? max rise and fall time: 3.0ns max (measured between 10% and 90%) pulse width: 500ns (1s for - 500 version) period: 1s (2s for - 500 version) output: each output is loaded with the equivalent of one 74f04 input gate. delay is measured at the 1.5v level on the rising and falling edge. note : above conditions are fo r test only and do not restrict the operation of the device under other data sheet conditions.
DS1100L 5 of 7 figure 3. test circuit table 1. DS1100L part number delay part DS1100L - xxx nominal delays (ns) tap 1 tap 2 tap 3 tap 4 tap 5 - 20 4 8 12 16 20 - 25 5 1 0 15 20 25 - 30 6 12 18 24 30 - 35 7 14 21 28 35 - 40 8 16 24 32 40 - 45 9 18 27 36 45 - 50 10 20 30 40 50 - 60 12 24 36 48 60 - 75 15 30 45 60 75 - 100 20 40 60 80 100 - 125 25 50 75 100 125 - 150 30 60 90 120 150 - 175 35 70 105 140 175 - 200 40 80 120 1 60 200 - 250 50 100 150 200 250 - 300 60 120 180 240 300 - 500 100 200 300 400 500
DS1100L 6 of 7 ordering information part temp ran ge pin - package DS1100Lz - xxx - 40 c to +85 c 8 so DS1100Lz - xxx/t&r - 40 c to +85 c 8 so DS1100Lz - xxx+ - 40 c to +85 c 8 so DS1100Lz - xxx+t - 40 c to +85 c 8 so DS1100Lu - xxx - 40 c to +85 c 8 max DS1100Lu - xxx/t&r - 40 c to +85 c 8 max DS1100Lu - xxx+ - 40 c to +85 c 8 max DS1100Lu - xxx+t - 40 c to +85 c 8 max xxx denotes total time delay (ns) (see table 1). + denotes a lead(pb) - free/rohs - compliant package. t&r and t = tape and reel. package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so (150 mils) s8+4 21- 0041 90- 0096 8 max u8+1 21- 0036 90- 0092
DS1100L 7 of 7 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change t he circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products. revision history revision date description pages changed 3/11 c hanged sop package ty pe to max; updated the absolute maximum ratings section; added the customer support email address to the electrical characteristics note 4; added the ordering information and package information tables 1? 6
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